Selected Publications:
Design Automation for VLSI IC and Bio/Nano Architectures
- G. Blakiewicz and M. Chrzanowska-Jeske, "Supply Current Spectrum Estimation of Digital Cores at Early Design," accepted to ET Circuits, Devices & Systems (formerly IEE Proceedings - Circuits, Devices and Systems), April 2007.
- Tao Wan and M. Chrzanowska-Jeske, "A Novel Net-Degree Distribution Model and its Application to Floorplanning Benchmark Generation," accepted to Integration, the VLSI Journal, September, 2006.
- J. S. Zhang, A. Mishchenko, Robert Brayton and M. Chrzanowska-Jeske "Symmetry Detection for Large Boolean Functions Using Circuit Representation, Simulation and Satisfiability," Proceedings of the IEEE Design Automation Conference, DAC06. July 2006.
- J. S. Zhang, M. Chrzanowska-Jeske, A. Mishchenko J, Burch, "Linear Cofactor Relationships in Boolean Functions,"the IEEE Trans. On CAD on Integrated Circuits and Systems, vol. 25, no 6, pp. 1011- 1023, June 2006.
- Alan Mishchenko, Jin S. Zhang, Subarna Sinha, Jerry R. Burch, Robert Brayton, and Malgorzata Chrzanowska-Jeske, "Using Simulation and Satisfability to Compute Flexibilities in Boolean Networks," the IEEE Trans. On CAD on Integrated Circuits and Systems, vol. 25, no. 5, pp. 743-755, May, 2006.
- M. Chrzanowska-Jeske, A. Mishchenko, "Synthesis for Regularity using Decision Diagrams," Proceedings of IEEE ISCAS’05 , May 2005.
- Jin S. Zhang, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Jerry R. Burch , "Fast Computation of Generalized Symmetries in Boolean Functions," Proceedings of IEEE ASP-DAC, January 2005.
- M.Jeske, G. Blakiewicz, M. Chrzanowska-Jeske, B. Wang, "Substrate Noise-Aware Floorplanning for Mixed-Signal SOCs," Proceedings of the International Symposium on Circuits and Systems, 2004.
- F. Rafiq, M. Chrzanowska-Jeske, H. H. Yang, M. Jeske, N. Sherwani, "Integrated Floorplanning with Buffer/Channel Insertion for Bus-Based Designs," IEEE Trans on Computer-Aided-Design, Vol. 22, nr. 6, pp 730-741, 2003.
- Y. Xia, M. Chrzanowska-Jeske, B. Wang M. Jeske, "Using a Distributed Rectangle Bin-Packing Approach for Core-based SoC Test Scheduling with Power Constraints," Proceedings of the IEEE International Conference on Computer-Aided Design, ICCAD, 2003.
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Jeff Hoffman & Don Tornquist have been chosen for the 2009-2010 ECE Undergraduate Honors Program. The program enables undergraduates to go beyond their normal studies to work with faculty in the area of their choice: research, entrepreneurship or innovation.
Dr. Robert Daasch has won the Semiconductor Research Corporation 2009 Technical Excellence Award. It is the second highest research award in the SRC. The Technical Excellence Award was established as an incentive and recognition program for research of exceptional value to GRC members. Authorized by the Board of Directors in December 1991, the award is intended to complement the Inventor Recognition Award. The Technical Excellence Award is shared among key contributors for innovative technology that significantly enhances the productivity/
competitiveness of the semiconductor industry. To date 25 research efforts have received the award. The 2008 Technical Excellence Award was presented to a team of researchers from Portland State University led by Professor W. Robert Daasch, and supported by students Liwei Ning (PhD 2009), and Amit Nahar (MS 2006) for their research, "Burn-in Reduction: Improving Outlier Screening".
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